              Atari "Sally" (6502) Instruction Set

Instruction Descriptions (listed alphabetically):
MNEMONIC             OPERATION              N  Z   C   I   D  V
   ADC    A' = A + M + C 1                  X  X   X   .   .  X
  ANC *   A' = A /\ M                       X  X  A'   .   .  .
                                                   7
   AND    A' = A /\ M                       X  X   .   .   .  .
  ARR *   A' = ((A /\ M) >> 1) + (C * 80)   X  X  A'   .   .  X
                                                   6          4
   ASL    M' = M << 1                       X  X   X   .   .  .
  ASR *   A' = (A /\ M) >> 1                X  X   X   .   .  .
  ASX *   X' = (X /\ A) - M                 X  X   X   .   .  .
  AX7 *   M' = A /\ X /\ 07                 .  .   .   .   .  .
  AXE *   A' = (A \/ EE) /\ X /\ M          X  X   .   .   .  .
   BCC    IF NOT C THEN PC' = PC + M        .  .   .   .   .  .
   BCS    IF C THEN PC' = PC + M            .  .   .   .   .  .
   BEQ    IF Z THEN PC' = PC + M            .  .   .   .   .  .
   BIT    A /\ M                           M7  X   .   .   . M6
   BMI    IF N THEN PC' = PC + 1            .  .   .   .   .  .
   BNE    IF NOT Z THEN PC' = PC + 1        .  .   .   .   .  .
   BPL    IF NOT N THEN PC' = PC + 1        .  .   .   .   .  .
   BRK    *(100 + S--) = PC15-8             .  .   .   .   .  .
          *(100 + S'--) = PC7-0
          *(100 + S''--) = P
          PC' = *(FFFE)
          P4' = 1
   BVC    IF NOT V THEN PC' = PC + 1        .  .   .   .   .  .
   BVS    IF V THEN PC' = PC + 1            .  .   .   .   .  .
   CLC    C' = 0                            .  .   0   .   .  .
   CLD    D' = 0                            .  .   .   .   0  .
   CLI    I' = 0                            .  .   .   0   .  .
   CLV    V' = 0                            .  .   .   .   .  0
   CMP    A - M                             X  X   X   .   .  .
   CPX    X - M                             X  X   X   .   .  .
   CPY    Y - M                             X  X   X   .   .  .
  DCP *   M' = M - 1                        X  X   X   .   .  .
          A - M'
   DEC    M' = M - 1                        X  X   .   .   .  .
   DEX    X' = X - 1                        X  X   .   .   .  .
   DEY    Y' = Y - 1                        X  X   .   .   .  .
   EOR    A' = A \^/ M                      X  X   .   .   .  .
   INC    M' = M + 1                        X  X   .   .   .  .
   INX    X' = X + 1                        X  X   .   .   .  .
   INY    Y' = Y + 1                        X  X   .   .   .  .
  ISB *   M' = M + 1                        X  X   X   .   .  .
          A' = A - M' - ~C 1
  JAM *       These instructions never
          finish; the CPU is locked in an
            infinite cycle. Coprocessors
           continue to function normally.
   JMP    PC = Mshort                       .  .   .   .   .  .
   JSR    *(100 + S--) = (PC - 1)15-8       .  .   .   .   .  .
          *(100 + S'--) = (PC - 1)7-0 2
          PC = Mshort
  LAS *   A' = S /\ M                       X  X   .   .   .  .
          S' = S /\ M
          X' = S /\ M
  LAX *   A' = M                            X  X   .   .   .  .
          X' = M
   LDA    A' = M                            X  X   .   .   .  .
   LDX    X' = M                            X  X   .   .   .  .
   LDY    Y' = M                            X  X   .   .   .  .
   LSR    M' = M >> 1                       0  X   X   .   .  .
   NOP    Nothing is done                   .  .   .   .   .  .
   ORA    A' = A \/ M                       X  X   .   .   .  .
   PHA    *(100 + S--) = A                  .  .   .   .   .  .
   PHP    *(100 + S--) = P                  .  .   .   .   .  .
   PLA    A' = *(100 + ++S)                 X  X   .   .   .  .
   PLP    P' = *(100 + ++S)                RE
                                           ST
                                           OR
                                           ED
  RLA *   M' = (M << 1) + C                 X  X   X   .   .  .
          A' = A /\ M'
   ROL    M' = (M << 1) + C                 X  X   X   .   .  .
   ROR    M' = (M >> 1) + (C * 80)          X  X   X   .   .  .
  RRA *   M' = (M >> 1) + (C * 80)          X  X   X   .   .  .
          A' = A + M' + C' 1 3
   RTI    P' = *(100 + ++S)                RE
          PC7-0 = *(100 + ++S) 2           ST
          PC15-8 = *(100 + ++S)            OR
                                           ED
   RTS    PC7-0' = *(100 + ++S)             .  .   .   .   .  .
          PC15-8' = *(100 + ++S) 2
          PC'' = PC' + 1
  SAX *   M' = A /\ X                       .  .   .   .   .  .
   SBC    A' = A - M - ~C 1                 X  X   X   .   .  .
   SEC    C' = 1                            .  .   1   .   .  .
   SED    D' = 1                            .  .   .   .   1  .
   SEI    I' = 1                            .  .   .   1   .  .
  SLO *   M' = M << 1                       X  X   X   .   .  .
          A' = A \/ M'
  SRE *   M' = M >> 1                       X  X   X   .   .  .
          A' = A \^/ M'
   STA    M' = A                            .  .   .   .   .  .
   STX    M' = X                            .  .   .   .   .  .
   STY    M' = Y                            .  .   .   .   .  .
  SX7 *   M' = X /\ 07                      .  .   .   .   .  .
  SY7 *   M' = Y /\ 07                      .  .   .   .   .  .
   TAX    X' = A                            X  X   .   .   .  .
   TAY    Y' = A                            X  X   .   .   .  .
   TSX    X' = S                            X  X   .   .   .  .
   TXA    A' = X                            X  X   .   .   .  .
   TXS    S' = X                            .  .   .   .   .  .
   TYA    A' = Y                            X  X   .   .   .  .
  XEA *   A' = (A \/ EE) /\ M               X  X   .   .   .  .
          X' = (A \/ EE) /\ M
  XS7 *   S' = A /\ X                       .  .   .   .   .  .
          M' = S' /\ 07
Notes:
  * Undocumented instruction. The behavior of these opcodes was
  observed on an Atari 800. It may vary with other 6502-based
  CPU's.
  1 In decimal mode, N and V are set after the high-order nibble
  is added or subtracted but before it is decimal-corrected,
  according to binary rules. Z is always set according to binary
  mode, not decimal. When decimal-correcting a nibble for
  addition, 6 is added if (nibble >= A) \/ C', and C'' = C' \/
  (nibble + 6 >= 10). Thus, F + F in decimal mode is 14, not 24.
  When decimal-correcting a nibble for subtraction, 6 is
  subtracted if ~C', and C'' = C' \/ (nibble - 6 < 0). Also,
  decimal correction can result in nibbles ranging from A-F; for
  example, C + D results in 19 before correction, 1F after.
  2 The value stored for the JSR operation is one byte prior to
  the address of the next instruction. However, the value stored
  for interrupts is the exact address of the next instruction.
  3 The carry bit is used twice in this operation: once for the
  rotate, and then the new value is used in the addition,
  creating the final value.
  4 V is set according to the function: (A6 /\ M6) \^/ (A7 /\
  M7).

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