Guus Assmann (who should be well known via SAG* or ABBUC) talked at the JHV** 2002 about one of his Atari 8Bit projects. Because it is a very interesting one, I have done this page for him. All required files (e.g. schematics and routing) can be found on this page below. For questions, feedback, etc. please contact the developer Guus Assmannn via Email  (dutch, german, english language). The Project:

65C02 - A new CPU inside the Atari XL/XE + a Real-Time-Clock
 We will replace the CPU 6502C in the Atari with a 65C02. Furthermore we add a Real Time Clock and  a  Parallel-Printer-Port and leave options for an Upgrade up to 65C816 CPU.

65C02

   Pictures from 65C02-Board

   A new CPU, how and why?

   Schematic and Partlist

   The 65C816 Upgrade

   Download and Email

   Other Projects of Guus Assmann



Another Site for the 65C02 on http://www.retrobits.net  => Atari 8-bit => Projects => XL/XE Alternate CPU

*  SAG => Foundation of Atari Users in the Netherlands  /  ABBUC => Atari Bit Byter User Club in Germany

** JHV = "Jahres-Haupt-Versammlung", the name for the annual meeting (and atari-fair) of the german club ABBUC



And here some Pictures from the dutch "Atari-Magazin" in 1987:


65C02-PCB
The Board

Note: the ribbon cable in the pictures is to support a memory upgrade, and not necessary for this mod.
Item
Pieces of the Board
65C02-Layout
Layout
 

Design history: (the original Text)


 The schematics of the old 400 / 800 contain the CPU part already. So this was just simple to do. And back in 1986 it was expensive to buy an Atari CPU. The 65C02 was less expensive and could also be buffered. This is useful if you want to add more hardware to the system. And more hardware was something that was wanted. And when a PCB has to be designed, why not do something more. So also a Real Time Clock was added. But this called for an extra PIA. This could be done in the cartridge port also, but this would be used up then. And if someone decides to open up his computer, why not do more at once.  This extra PIA would then have one port left. In turn it would be good to use this port for a centronics printer driver. This driver would be a chance to call for a contest.

 Why hardware was needed? It's good material to get a magazine filled. And the ATARI Magazine, by the SAG (Foundation of Atari Users in the Netherlands) could use some good information. In the interest of 7000 users it's nice to help keep prices low. This has been the philosophy of the SAG all the time. If you publish something and offer parts, it keeps prices low.


A new CPU ?  How and Why ?


Characteristics from the Board

 - A 65C02 CPU with buffered address and data bus
 - A second PIA. One port with a RTC. The second port with buffering to create a printer port.
 - Device driver software for the Real Time Clock. (Including source code- only on paper yet, is tested.)
 - Board replaces the original CPU and PIA. Both have to be removed, the PCB occupies their previous location, PIA can be reused on the PCB.
 - The CPU may also be replaced by a 65C816 with some minor modifications
    (I'll check).
 - PCB may be cut to only use CPU or PIA.

Why replace the CPU ?

 - The original 6502 and also the ATARI 6502C have some minor bugs.
 - The 65C02 fixes these and also adds some very useful instructions.
 - Also now the CPU address and data busses are buffered.
 - The 65C02 is CMOS and draws less current.
 - Some Atari CPU's, manufactured in Mexico are defective. They are temperature sensitive and make the computer hang

Why a second PIA?

 - To be able to use the RTC and add a printer port, without compromising compatibility. If the extension is not wanted, don't load drivers and it's not there.

This Text

Disadvantage of the 65C02 CPU

Programs that use illegale Opcodes (means many Demo Programs and some newer Games) works not with the 65C02 CPU!


Schematics


65C02-Schematic

Explanation of Schematics

65C02 CPU in Atari, explanation of schematics.

First the easiest part, the extra PIA.
The PIA has a total of 3 Chip Select lines. The Atari only uses one, 
the pin 23 CS2 line which is active low. The other 2 are active high, 
pins 22 and 24 and are normally connected to VCC.
The PIA only uses four addresses but the MMU (Memory Management Unit) 
reserves 256 bytes in $D300 to $D3FF. To select an extra PIA, the 
A7 line is inverted by IC9, a 74LS04. The A7 line is connected to 
pin 9 of the inverter and comes out on pin 8. This inverted A7 is 
used to drive the "original" PIA pin 22, the CS0 line. The A7 line is 
used to drive the CS0 line of the extra PIA. The original PIA is now 
on $D300 to $D37F and the extra is on $D380 to $D3FF.
Note: When Using the second PIA U8 cut the Trace from the
Socket U7 Pin 22 to PIA U7 Pin 22.
(This can be done once more with the A6 line also. Pin 5 of U9 
inverter. The space is divided into four parts. D300 to D33F; D340 to 
D37F; D380 to D3BF and D3C0 to D3FF. The PIA Pin 24 should be used 
for this. Cut the trace connecting the PIA to the plug and connect 
the inverted A6 line to pin 24 for of the PIA's. All programs will 
work and the extra parts can be accessed at D340 to D37F and D3C0 to 
D3FF)

The RTC is an Oki MSM 5832.
It's connected to the PIA's port B. The source code makes clear how 
to use it and also explains how to write an Atari driver.

The other PIA port can be used to make a Centronics port to drive a 
printer. The data lines are buffered with a 74LS244 and the strobe 
and busy are buffered with the 74LS01 IC9.
See a data sheet on the 6520 or 6821 (Same chip) to find out how to 
program the PIA.

The next part is more difficult, the 65C02 Processor.
Both the original Atari 6502C and the C-Mos 65C02 have a limited 
drive capacity (Fan-out). This is one of the reasons for the buffers 
74F244 and 74F245. These buffers may also be 74LS or 74ALS. (74S is 
not tested but may also work)
The buffers may also be "Tri-stated" (Isolation between input and 
output) This is needed when the HALT line is activated by the ANTIC 
to signal the CPU that ANTIC wants the bus. Once HALT is active (low), 
the signal is latched by U2, half a 74LS74. The signal is latched on 
the Q1 clock going high. The inverted output of the latch goes to 
"high" and disables the buffers, the R/W line and the clock into the 
CPU. As the clock signal is stopped, the CPU "freezes" And it's a 
Static design, so there's no need for a clock signal to refresh 
registers. This feature was also build in the Atari 6502C Processor.
The last part is the generation of the Q1 and Q2 signal by the U2 
part 2. The LS02 port inverts the Q0 signal that was originally fed 
to the CPU. The Q0 and inverted Q0 drive the set and reset lines of 
the 74LS74 and this generates the non-overlapping clocks Q1 and Q2. 
(Not stopped by HALT as the processor signals would be) The timing 
is a bit critical here. Other 74 types may not work.

Note: To use a 65C816 at another clock speed, the input into the CPU 
should be changes and the 74LS74 left unchanged. This is being 
investigated.


Items required:       (PCB may be cut to only use CPU or PIA)


65C02 Upgrade:

  1 x IC 65C02 CPU
  1 x IC 74LS02
  1 x IC 74LS74
  2 x IC 74LS244
  1 x IC 72LS245
  3 x Drossel 10uH
  3 x Widerstand 1 Ohm
  2 x Kondensator 100nF
  1 x Stecker 40 pins DIL oder qualitts-Sockel mit Drhte

Real-Time-Clock:

  1 x IC MSM5832 RTC Chip (OKI)
  1 x IC 6520 oder 6821 (der zweite ist der vom Atari)
  1 x IC 74LS04
  5 x Widerstand 100K
  1 x Widerstand 1K
  1 x Kondensator 22 pF
  3 x Kondensator 100 nF
  1 x Drehkondensator 5-20 pF
  1 x Quartz 32,768 kHz Uhrenquartz.
  1 x Diode D1= AA119 oder andere Germanium oder Schottky Diode.
  1 x Diode D2= 1N4148
  1 x Elko 10uF / 16V
  1 x Stecker 40 pins DIL oder qualitts-Sockel mit Drhte.

Printer-Port:

  1 x 74LS244

----------------------------------------------------------------------------------------------------------------------

Upgrade with the 65C816 CPU


Die 65C816 CPU might give you further advantages:

The 65C816 CPU can be used with up to 14Mhz which is an enormous increase in power!

The 65C816 CPU has a linear adress range of 16MB. In 24 bit adressing, the upper 8 bits are banks, meaning 256 banks of 64kbytes each. But here is the question on how to make this compatible to the 130XE standard of port B.

The 65C816 CPU has two operation modes:
One emulation mode, where (after Reset) all instructions and adresses (adress modes) are usable.
Next a native mode, which allows the full use of the CPU via 16bit registers and block-move instructions.

These are the main advantages. The disadvantages are for example, that if doubling the clock speed the clock cycles have to be synchronized (extremely difficult!). The actual developer phase by Guus is a 65C816 which runs at normal clock speed.

Pins 1, 5, 7, 35, 38, 39 of the CPU do not connect.
Pin 3 via Pull up Resistor 10KOhm to +5V.
Pin 36 to Pin 5 from 74LS74 (latching Halt Signal)

The next step ist to double the clock speed of the CPU, whereby the clock cycles have to be synchronized.

(EOF)
